The present invention relates to a semiconductor manufacturing technique that reduces the cost and complexity of producing multiple undercut profiles in the same material. For example, the present invention provides a simplified etch process capable of generating two different undercut profiles in the same material, such as silicon dioxide or the like, using a single lithographic step during the manufacture of flat panel field emission display (FED) devices.
Conventional semiconductor techniques commonly utilize lithographic techniques to selectively place a pattern on a work piece during manufacture. For example, lithography may be used to apply a resist pattern over a layer of material such as silicon dioxide. An etching process then removes portions of the silicon dioxide that remain exposed after the photoresist pattern is printed over the silicon dioxide layer. Such an etching process allows a manufacturer to obtain a desired structure in the underlying material. The photoresist pattern is typically removed after etching and the work piece may be processed further by the deposition of additional material layers and further selective etchings. Mechanical operations such as chemical-mechanical planarization (CMP) and other processes may also be used in the manufacturing process.
One difficulty that has been encountered in prior manufacturing techniques is based on the requirement that the various layers of the semiconductor device be aligned with a relatively high degree of alignment accuracy. Unfortunately, lithographic printing techniques may be somewhat limited in alignment accuracy and resolution. For example, one resist pattern may be slightly offset relative to the underlying work piece. If a subsequent resist layer is also offset, possibly in a direction different from the first offset direction, then a defect may result, lowering the effective yield of the manufacturing process. Similarly, the resolution of the printing process might not allow for fine detail that would permit certain structures to be obtained. Thus, it may be necessary to introduce a relatively large xe2x80x9cmargin of errorxe2x80x9d into the manufacturing process by producing features that are large enough to accommodate misalignments. Of course, this limits the degree of miniaturization that may be achieved in the manufacturing operation.
Each photolithographic/etching step entails the expenditure of time and resources, adding to the costs of manufacture. Moreover, each photolithographic/etching step carries with it the possibility of errors or defects and, consequently, potentially reduced yields. Thus, from the standpoint of size, cost and yield, it is desirable to minimize the number of photolithographic steps performed during the manufacturing operation.
It is a primary objective of the present invention to provide a simplified etch process that avoids difficulties encountered in prior art manufacturing techniques, and is capable of producing two different undercut profiles in a work piece using a single lithographic step. The present invention may find application, for example, in the manufacture of flat panel field emission displays (FEDs). However, the invention is not limited to FEDs and may be used in connection with manufacturing processes for other devices such as micromachines that may require undercut structures within a base material.
In accordance with one aspect of the present invention, a method for producing an undercut profile in a work piece includes forming a resist pattern on a top surface of the work piece. Apertures in the resist pattern expose portions of the work piece where an undercut profile is to be created. A first etch is performed on the portions of the work piece exposed by said resist pattern to remove material from the work piece and to create a selected undercut in the work piece. A second etch is then performed on the work piece to remove additional material from the work piece and to produce a polymer film which at least partially fills the selected undercut created by the first etch. A third etch removes yet more material from the work piece and creates an additional selected undercut in the work piece. Finally, the resist pattern is stripped and the polymer film is removed.
The first etch and the third etch may each be a wet etch process, and the second etch may be a polymerizing dry etch process. The work piece may be a single layer of material or may include a plurality of material layers wherein at least two of the material layers are formed of the same material.
In accordance with another aspect of the present invention, a simplified etch process capable of generating selected undercut profiles in a work piece performs a first wet etch of portions of the work piece to create a first undercut in the work piece. A polymer film is then formed over side surfaces of the first undercut to inhibit further etching of the first undercut during subsequent etching operations. Then, a second wet etch of portions of the work piece is performed to create a second undercut in the work piece. In a preferred implementation the polymer film is formed by a polymerizing dry etch. The etching steps may be controlled by a resist pattern formed on the work piece prior to etching. The resist pattern and the polymer film are then removed following the final etching step.
In accordance with yet another aspect of the present invention, a method used in the manufacture of a flat panel field emission display forms a resist pattern over a field emission display base structure which includes a plurality of material layers arranged on a substrate, with at least a first material layer and a second material layer being formed of the same material. The resist pattern has a plurality of apertures that define portions of the base structure that are to be etched. The first material layer is etched at the defined portions with an etching process that creates an undercut in the first material layer. The defined portions of the base structure are etched with a polymerizing etch process to form a polymer film at the undercut made in the first material layer. The second material layer is then etched at the defined portions with an etching process that creates an undercut in the second material layer. After the second material layer is etched, the polymer film and the resist pattern are removed.
In one implementation, the first material layer and the second material layer are insulation layers formed of silicon dioxide. In that case, the steps of etching the first and second material layers are each wet etch processes utilizing hydrogen fluoride. Moreover, the base structure may include a top passivation layer of silicon nitride. In that case, a dry etch of the silicon nitride layer is performed at the portions of the base structure defined by the apertures in the resist pattern prior to etching the first layer.
In accordance with yet another aspect of the present invention, a non-horizontal surface of a first material is defined within a semiconductor device. The semiconductor device is exposed to a first material-etching substance and the non-horizontal surface is protected from the material-etching substance. For example, the non-horizontal surface may be protected by forming a polymer on the surface.
A further aspect of the invention provides a method for profiling a semiconductor device by providing a patterned mask over the semiconductor material, performing a first etch of the material while guiding the first etch with the mask, adding a polymer to an etched portion of the material, and performing a second etch of the material while guiding the second etch with the mask and the polymer. Additionally, in one aspect of the present invention, a method is provided for producing multiple undercut profiles within a semiconductor device. A plurality of levels is defined within the semiconductor device using a plurality of etches. A polymer is generated on a side of at least one of the levels after at least one etch of the plurality of etches, and at least one etch of said plurality of etches is performed after the polymer is generated. As an example, the plurality of layers in the semiconductor device may be a plurality of layers within an insulator.
These and other aspects of the present invention are set forth in greater detail below and in the appended claims. It should be noted that the foregoing description of the various aspects of the invention is not exhaustive and should not be considered to limit the present invention. Instead, the invention is intended to cover various modifications and equivalent arrangements included within the scope of the claims.